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Ordering number:ENN3661B
CMOS IC
LC7219, 7219M
PLL Frequency Synthesizers
Overview
The LC7219 and LC7219M are high-performance, phaselocked loop (PLL) frequency synthesizer ICs that operate over the AM and FM radio wavebands. They feature excellent frequency tracking, making them ideal as reference frequency sources for use in AM/FM tuners, television and audio-video equipment, and high-quality car-stereo applications. The LC7219 and LC7219M operate from a 5 V supply and are available in 24-pin DIPs and 24-pin MFPs, respectively.
Package Dimensions
unit:mm 3067A-DIP24S
[LC7219]
21.0 24 13
7.62 6.4
1
12 0.9
3.3 3.9max (3.25)
Features
* Programmable divider. * General-purpose universal counter. (The IF signal count must be used together with the SD (station detect) signal from IF-IC). * Unlock detector. * 8 Hz real-time clock output. * Ten selectable reference frequencies. * 400 kHz microcontroller system-clock output. * Swallow counter. * Shift register. * 5 V supply. * 24-pin DIP and 24-pin MFP.
(0.71)
1.78
0.48
0.95
0.51min
SANYO : DIP24S
unit:mm 3045B-MFP24
[LC7219M]
24 13
15.3
0.35
1.27
0.67
0.1
SANYO : MFP24
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
71901TN (KT)/D2593JN/1142JN No.3661-1/12
2.5max
0.15
2.15
0.75
1
12
9.0 10.5
7.9
0.25
LC7219, 7219M
Block Diagram
SYC 6
XIN XOUT FMIN
1 24 19
REFERENCE DIVIDER
PHASE DETECTOR CHARGE PUMP
21 22
PD1 PD2 HCTR
1 2
SWALLOW COUNTER 1/16, 1/17 4BIT
16
AMIN
18
12BIT PRORAMABLE DIVIDER
15
LCTR
CE DI CL DO
2 3 4 5 9 10 11 12 13 14 17 7 IN0 8 IN1 SHIFT REGISTER LATCH UNIVERSAL COUNTER 20 23 VDD VSS
OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6
Pin Assignment
Top view
Pin Description
Number 1 2 3 4 5 6 7, 8 9 to 14, 17 15 16 18 19 20 21, 22 23 24 Name XIN CE DI CL DO SYC IN0, IN1 OUT0 to OUT6 LCTR HCTR AMIN FMIN VDD PD1, PD2 VSS XOUT 7.2MHz crystal oscillator input Chip-enable input Data input from microcontroller Clock input Data otuput to microcontroller 400kHz, 66% duty cycle, system-clock output Shift register data inputs Shift register data outputs Period or frequency measurement general-purpose counter input Frequency measurement general-purpose counter input AM band VCO signal input FM band VCO signal input Supply voltage Phase-detector charge pump outputs Ground 7.2MHz crystal oscillator output Description
No.3661-2/12
LC7219, 7219M Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0V
Parameter Maximum supply voltage CE, CL, DI, IN0 and IN1 input voltage Input voltage for all other pins DO and SYC output voltage OUT1 and OUT2 output voltage OUT0 and OUT3 to OUT6 output voltage Output voltage for all other pins Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN1 VIN2 VOUT1 VOUT2 VOUT3 VOUT4 Pd max Topr Tstg Conditions Ratings - 0.3 to +7.0 - 0.3 to +7.0 - 0.3 to VDD+0.3 - 0.3 to +7.0 - 0.3 to VDD+0.3 - 0.3 to +15.0 - 0.3 to VDD+0.3 350 (LC7219) 350 (LC7219M) - 40 to +85 - 55 to +125 Unit V V V V V V V mW C C
Reommended Operating Conditions at Ta = 25C, VSS = 0V
Parameter Supply voltage range Supply voltage range for crystal oscillator operation CE, CL, DI, IN0 and IN1 high-level input voltage LCTR high-level iutput voltage CL, CE, DI, IN0 and IN1 low-level input voltage LCTR low-level iutput voltage DO and SYC output voltage OUT0 and OUT3 to OUT6 output voltage XIN input frequency FMIN input frequency*1 AMIN input frequency HCTR input frequency*2 Symbol VDD1 VDD2 VIH1 VIH2 VIL1 VIL2 VOUT1 VOUT2 fIN1 fIN2 fIN3 fIN4 VDD VDD Period measurement, VDD=4.5 to 6.5V Period measurement, VDD=4.5 to 6.5V Conditions Ratings min
4.5
typ
max 6.5 6.5 6.5 VDD
0.7 0.3VDD
Unit V V V V V V V V MHz MHz MHz MHz
3.5
2.2
0.7VDD 0 0
6.5 13 Sine wave, capacitive coupling, VDD=3.5 to 6.5V Sine wave, capacitive coupling, VDD=4.5 to 6.5V See table 5 Sine wave, capacitive coupling, VDD=4.5 to 6.5V See table 5 Priod measurement, sine wave, capacitive coupling, VDD=4.5 to 6.5V Frequency measurement, sine wave, capacitive coupling, VDD=4.5 to 6.5V Priod measurement, pulse wave DC coupling, VDD=4.5 to 6.5V 1.0 10 0.5 10 15 0.001 3.0 0.5 0.07 0.07 0.07 0.07 7.2 7.2 8.0 130 40.0 60 500
LCTR input frequency Crystal oscillator frequency XIN rms input amplitude FMIN rms input amplitude*1 AMIN rms input amplitude HCTR rms input amplitude*2 LCTR rms input amplitude
fIN5 fXTAL VIN1 VIN2 VIN3 VIN4 VIN5
KHz 20.0 8.0 1.5 1.5 1.5 1.5 1.5 MHz Vrms Vrms Vrms Vrms Vrms
XIN- XOUT: Crystal impedance 50 Sine wave, capacitive coupling, VDD=4.5 to 6.5V Sine wave, capacitive coupling, VDD=4.5 to 6.5V Sine wave, capacitive coupling, VDD=4.5 to 6.5V
Frequency measurement, VDD=4.5 to 6.5V Frequency measurement, sine wave, capacitive coupling, VDD=4.5 to 6.5V
Notes 1. fIN2=10 to 160MHz for VIN2=0.1V(min) 2. fIN4=10 to 70MHz for VIN4=0.1V(min)
No.3661-3/12
LC7219, 7219M
Electrical Characteristics at Ta = -40 to +85C, VSS = 0V
Parameter XIN internal resistance FMIN internal resistance AMIN internal resistance HCTR internal resistance LCTR internal resistance LCTR hysteresis width CE, CL and DI high-level input current IN0 and IN1 high-level input current XIN high-level input current AMIN and FMIN high-level input current HCTR and LCTR high-level input current CE, CL and DI low-level input current IN0 and IN1 low-level input current XIN low-level input current FMIN and AMIN low-level input current HCTR and LCTR low-level input current OUT1 to OUT2 high-level output voltage PD1 to PD2 high-level output voltage OUT1 to OUT2 low-level output voltage PD1 to PD2 low-level output voltage OUT3 to OUT6 low-level output voltage OUT0 low-level output voltage DO low-level output voltage SYC low-level output voltage OUT0 and OUT3 to OUT6 output off leakage current DO output off leakage current SYC output off leakage current PD1 and PD2 low-level off leakage current PD1 and PD2 high-level off leakage current FMIN and HCTR input capacitance Supply current Symbol Rf1 Rf2 Rf3 Rf4 Rf5 VH IIH1 IIH2 IIH3 IIH4 IIH5 IIL1 IIL2 IIL3 IIL4 IIL5 VOH1 VOH2 VOL1 VOL2 VOL3 VOL4 VOL5 VOL6 IOFF1 IOFF2 IOFF3 IOFFL IOFFH CIN IDD 0.1VDD VIN=6.5V VIN=VDD VIN=VDD VIN=VDD VIN=VDD VIN=VSS VIN=VSS VIN=VSS VIN=VSS VIN=VSS IO=1mA IO=0.5mA IO=1mA IO=0.5mA IO=5mA IO=1mA IO=5mA IO=0.5mA, VDD=3.5 to 6.5V VO=13V VO=6.5V VO=6.5V VO=VSS VO=VDD 1 fIN2=130MHz, VIN2=70mV, 7.2MHz, crystal oscillator running, inputs grounded outputs open PLL inhibited, oscillator running, inputs grounded, outputs open VDD- 1 VDD- 1 1.0 1.0 1.0 1.0 1.0 1.0 5 5 5 10.0 10.0 3 30 Conditions Ratings min typ 1 500 500 500 500
0.6VDD
max
Unit M k k k k V A A A A A A A A A A V V V V V V V V A A A nA nA pF mA mA 5 5
20 40 40 5 5 20 40 40
0.01 0.01 2 20 1.0
Functional Description
Serial Data Input The LC7219 and LC7219M are initialized by 36-bit data on the serial data input, DI, after power-on as shown in figure 1 and table 1.
Figure 1. Input data format
No.3661-4/12
LC7219, 7219M
Table 1. Input data bits
Bits 1 to 16 Name D0 to D15 Description Programmable divider ratio D15 is the msb. The lsb is determined by the setting of the DV and SP flags as shown in table 6. D0 to D3 are ignored if D4 is the lsb. Output port data Data bits O0 to O6 are latched into the OUT0 to OUT6 ports, respectively. When a data bit is 1, the corresponding output pin is LOW, and when 0, HIGH. These outputs can be used for frequency band selection. If TB is 1, the O0 bit is ignored and the 8 Hz timebase signal is output on OUT0. General-purpose counter enable When CTEN is 0, the 20-bit general-purpose counter is reset and the HCTR and LCTR inuts are pulled to ground. When the CTEN flag is 1, the counter is enabled and the signal on HCTR or LCTR, selected by SC, is measured. Note that the general-purpose counter output should be transferred to the external controller before CTEN is set to 0. Reference frequency select Bits R0 to R3 disable the PLL or select the reference frequency as shown in table 2. When the PLL is disabled, the programmable divider is stopped, AMIN and FMIN are pulled to ground, and the charge-pump outputs become high impedance. Divider select and sensitivity select DV select the local-oscillator input FMIN or AMIN. SP selects the input frequency range when AMIN is selected as shown in table 6. General-purpose counter input select and frequency/period measurement select SC selects the general-purpose counter input. SF selects frequency or period measurement when LCTR is selected as shown in table 7. When HCTR is selected, the counter is in frequency measurement mode. General-purpose counter time interval select Bit GT selects the measurement time interval or the number of periods to be measured. When GT=1, then 30 ms or 2 periods are selected, and when GT=0, 60 ms or 1 period is selected. Timebase output enable When TB is 1, the 8 Hz, 40% duty cycle timebase signal is output on OUT0. The O0 bits is ignored. Test control bits Bits T0 to T1 are used for device testing and are set to 0 for normal operation. Related bits DV, SP
17 to 23
O0 to O6
TB
24
CTEN
SC, SF, GT
25 to 28
R0 to R3
29, 30
DV, SP
31, 32
SC, SF
CTEN, GT
33
GT
CTEN, SC, SF
34 35, 36
TB T0, T1
O0
The reference frequency is selected by bits R0 to R3 as shown in table 2. Table 2. Reference frequency selection
R0 0 0 0 0 0 0 0 0 R1 0 0 0 0 1 1 1 1 R2 0 0 1 1 0 0 1 1 R3 0 1 0 1 0 1 0 1 Reference frequency (kHz) 100 50 25 25 12.5 6.25 3.125 3.125
Table 2. Reference frequency selection-continued
R0 1 1 1 1 1 1 1 1 R1 0 0 0 0 1 1 1 1 R2 0 0 1 1 0 0 1 1 R3 0 1 0 1 0 1 0 1 PLL inhibit Reference frequency (kHz) 10 9 5 1
Serial Data Input Timing The timing for the serial data input is shown in figure 2. The first four bits, A0 to A3, are the mode select bits. In 36-bit transfer mode, the final data bits are T0 and T1, and in 24-bit transfer mode, O6 and CTEN.
Figure 2. Input timing Note t11.5s, t20s, t31.5s, t4<1.5s
No.3661-5/12
LC7219, 7219M
Serial Data Output The LC7219 and LC7219M both have an internal 28-bit shift register that comprise two bits representing the state of IN0 and IN1 (I0 and I1, respectively), a 20-bit general-purpose counter address (C0 to C19) and unlock flags (UL0 to UL3) as shown in table 3. The shift register contents are clocked out on DO when the serial data output mode is selected as shown in figure 3. The internal circuit of outputs DO and OUT0 to OUT6 are shown in figure 4. Table 3. Shift register data
Bits 1, 2 3, 4 5 to 24 C0 to C19 Name I0, I1 Input port data I0 is the state of IN0, and I1, the state of IN1. Invalid General-purpose counter value Bits C0 to C19 are the latched value of the 20-bit counter. C19 is the msb. PLL unlock status bits Bits UL0 to UL3 are the latched data from the unlock detector circuit. When the phase error exceeds the value for a given bit as shown below for a 7.2MHz crystal, the bit is set. UL0 is set when ERROR 1.1s UL1 is set when ERROR 2.2s UL2 is set when ERROR 3.3s UL3 is set when ERROR 0.55s Description
25 to 28
UL3 to UL0
Figure 3. Shift register data format
Figure 4. Output driver internal circuits Serial Data Output Timing The timing for the serial data output is shown in figure 5. Bits A0 to A3 are the mode select bits. When CE goes HIGH, I0 is output on DO, and each subsequent data bit is output on the falling edge of CL. CE should be held HIGH for 27 clock cycles to allow all data to be output. In serial data output mode, DO is forced HIGH when CE goes LOW as shown in figure 5. DO goes LOW when the status of IN0 changes. In frequency or period measurement modes, DO goes LOW when frequency or period measurement is completed.
Note t11.5s, t20s, t31.5s, t5<1.5s
Figure 5. Output timing
No.3661-6/12
LC7219, 7219M
Serial Bus Data Transfer The LC7219 and LC7219M can both transfer data in three different modes-36-bit input data transfer, 24-bit input data transfer and 28-bit output data transfer. The transfer mode is selected by the four data bits on DI immediately prior to CE going HIGH as shown in figure 6 and table 4. These bits are synchronized to the clock and are latched into the mode register on the rising edge of CE. Figure 6. Transfer mode select Table 4. Mode selection
Mode 36-bit serial data input A3 0 A2 0 A1 0 A0 1 Description All bits of the control data are clocked in on Dl. This mode sould be used after power-up to initialize the device. It can also be used to modify the values of bits R0 to R1. 24 bits of the control data are clocked in on Dl. This mode is used to input the programmable divier ratio bits, the output port bits and the general-purpose counter enable bit. Data is output on DO. The data comprises the input data, the generalpurpose counter value and the PLL unlock flags.
24-bit serial data input serial data output
0 0 0
0 0 0 1 0 1
1 1 0 x x x
0 1 0 x x x
Illegal
0 1 1
Data cannot be transferred.
Note x = don't care Programmable Divider The configurration of the programmable divider is shown in figure 7. Input mode selection is shown in table 5.
Figure 7. Programmable divider
Table 5. Programmable divider selection
DV 1 0 0 SP x 1 0 Input frequency range (MHz) 10 to 160 2 to 40 0.5 to 10.0 1/2 divider - - 1/16 and 1/17 pulse swallower - 12-bit programmable divider Input port FMIN AMIN AMIN
Note x = don't care When an FM signal is input on FMIN, the actual divider ratio is double the set ratio. For channel steps of 1, 5 and 9 kHz, a 3.6MHz crystal should be used. The programmable divider ratio is determined by the setting of the DV and SP bits as shown in table 6.
Table 6. Divider ratio settings
DV 1 0 0 SP x 1 0 lsb D0 D0 D4 Set ratio 256 to 65535 256 to 65535 4 to 4096 Actual ratio Twice set ratio Set ratio Set ratio
Note x = don't care
No.3661-7/12
LC7219, 7219M
General-purpose Counter The 20-bit general-purpose counter is used for both frequency and period measurement as shown in figure 8. The measurement mode is selected by bits SC and SF as shown in table 7. The counter value is output on DO with the msb first.
Figure 8. General-purpose counter Table 7. General-purpose counter mode selection
SC 1 0 0 SF x 1 0 Input port HCTR LCTR LCTR Parameter Frequency measurement (sine wave) Frequency measurement (sine wave) Period measurement (pulse wave)
Note x = don't care In frequency measurement mode, the input cycles during a 30 or 60 ms interval are counted. Either LCTR or HCTR can be selected as the counter input. In period measurement mode, LCTR is the single input, and the 900kHz cycles in one or two periods of the LCTR signal are counted. The counter starts when the CTEN flag is set. The serial input data is latched in on the falling edge of CE. The input data on HCTR or LCTR should be input within 10 ms of this transition. The period or frequency measurement count should be read while CTEN is still set to 1, as the counter is reset by setting CTEN to 0. CTEN should be set to 0 before each measurement. The LCTR signal is passed directly to the counter input. The HCTR signal is passed through a divide-by-eight prescaler. The actual HCTR frequency is, therefore, eight times the measured frequency. When the universal counter is used as the IF counter, the state of the IF-IC SD (station detect) signal must be checked by the microcontroller, and the IF counter buffer output turned on only after the SD signals are activated. Auto-search techniques using only the IF counter are not advisable since it is possible that the search can stop incorrectly at a location that does not have a station due to the IF counter buffer output leakage. DO goes HIGH when the CTEN flag is set to 1, and LOW when frequency or period measurement is completed. DO can be monitored to check for measurement completion. The timing for the general-purpose counter is shown in figure 9.
No.3661-8/12
LC7219, 7219M
Figure 9. General-purpose counter timing Using DO monitor IN0 If the general-purpose counter is not being used and CTEN is 0, DO can be used to monitor changes in the external input signal IN0 as shown in figure 10.
Figure 10. IN0 output monitoring timing
Notes 1. Specify serial data output. DO goes HIGH after data is output on DO and CE goes LOW. 2. DO goes LOW when IN0 changes.
No.3661-9/12
LC7219, 7219M
Using DO to monitor for measurement completion DO can be used to monitor for frequency or period measurement completion as shown in figure 11.
Figure 11. Measurement completion timing Notes 1. Setting CTEN to 1 sets DO HIGH and prevents IN0 from affecting DO. 2. DO goes LOW when the measurement is complete.
Phase-locked Loop
Reading the PLL unlock flags The PLL unlock flags are set on the rising edge of the internal ERROR signal and cleared on the rising edge of the CE signal. In serial data output mode, the flags set since the last rising edge of CE can be read. This is the interval t0 to t1 shown in figure 12. Each PLL unlock flag is set if the corresponding time interval is exceeded as follows.
UL0 is set when ERROR1.11s UL1 is set when ERROR2.22s UL2 is set when ERROR3.33s UL3 is set when ERROR0.55s
The flag values for different error ranges, where ERROR is the phase error for the 7.2MHz crystal, are as follows.
If ERROR<0.55s, UL=0000 If 0.55sERROR<1.11s, UL=1000 If 1.11sERROR<2.22s, UL=1001 If 2.22sERROR<3.33s, UL=1011 If 3.33sERROR, UL=1111
Figure 12. PLL unlock flag timing
No.3661-10/12
LC7219, 7219M
Application Notes The recommended crystal oscillator for the LC7219 and LC7219M is the Nihon Dempa Kogyo Co., Ltd. (NDK) LN-X-0702 (NR-18 type) or the LN-P-0001 (AT-51 type). The oscillator is connected as shown in figure 13.
Table 8. Device parameters vs. crystal frequency
Paraeter Timebase clock System clock Frequency measurement interval Period measurement check signal Reference frequencies 8Hz 400kHz 30/60ms Crystal frequency 7.2MHz 4Hz 200kHz 60/120ms 3.6MHz
900kHz 1kHz, 5kHz, 9kHz, 10kHz, 25kHz, 50kHz, 100kHz, t1 1.5s, t3 1.5s
450kHz 0.5kHz, 2.5kHz, 4.5kHz, 5kHz, 12.5kHz, 25kHz, 50kHz, t1 3s, t2 3s
Figure 13. Crystal oscillator connection The device parameters for crystal oscillator frequencies 3.6MHz and 7.2MHz are shown in table 8.
Data input/output timing
Typical Application Figure 14 shows a TV/AM/FM system using the IF counting system for electronic tuning.
Figure 14. TV/AM/FM system The FMIN, AMIN, HCTR, and LCTR inputs should be capacitively coupled using a capacitor in the range 50 to 100pF. These coupling capacitors should be as close as possible to their respective inputs to minimize the effects of stray capacitance. The IF signals measurement should be done afte the IF-IC SD (station detect) signal are activated. The circuit characteristics for each mode, TV, FM and AM, are shown in table 9. Table 9. Circuit characteristics
Mode TV FM AM DV 1 1 0 SP x x 0 Tuning frequency steps 50kHz 100kHz 10kHz RF frequency 637.75MHz (UHF) 90MHz 1,000kHz IF frequency 10.7MHz 10.7MHz 450kHz VCO frequency 648.45MHz 100.7MHz 1,450kHz PLL reference frequency 3.125kHz 50kHz 10kHz Programmable divider ratio 12,969 1,007 145
Note x = don't care
No.3661-11/12
LC7219, 7219M
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of July, 2001. Specifications and information herein are subject to change without notice.
PS No.3661-12/12

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